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general description the MAX8686 current-mode, synchronous pwm step- down regulator with integrated mosfets operates from a 4.5v to 20v input supply and generates an adjustable output voltage from 0.7v to 5.5v while delivering up to 25a per phase. the MAX8686 employs a peak current-mode architec- ture that operates with an adjustable switching frequency from 300khz to 1mhz. an adjustable current-limit thresh- old allows for optimization for different applications with different load currents. inductor current sense is achieved either using an external sense resistor or using a lossless inductor current-sense scheme. the foldback and hiccup current limit reduces the power dissipation during overload or short-circuit conditions and allows for autorecovery when the fault condition is removed. the MAX8686 offers the ability to start up monotonically even when there is a prebias output voltage. in addi- tion, an adjustable soft-start capability allows for a con- trolled turn-on. the MAX8686 features an accurate 1% reference and offers a reference input that allows for a higher accuracy reference to be used for voltage track- ing applications such as ddr memory. the MAX8686 can be paralleled (up to eight) together in a true multiphase mode to deliver up to 200a of out- put current. when operating in this mode, this device achieves better than 10% current balance between phases at full load. the MAX8686 supports program- mable phase shedding to improve system efficiency during light load conditions. other features include an enable input and a power-ok (pok) indicator used for power sequencing. the MAX8686 also features latch overvoltage protection that turns on the low-side mosfet when the output voltage exceeds 120% of the nominal voltage. the MAX8686 is offered in a thermally enhanced 40-pin, 6mm x 6mm tqfn package. applications pol power supplies module replacements telecom equipment networking equipment servers ddr memory features ? operating range from 4.5v to 20v input supply ? 1% reference voltage accuracy over temperature ? reference input (refin) for output tracking or system reference voltage ? adjustable switching frequency from 300khz to 1mhz ? single/multiphase operation delivers up to 25a/200a with integrated mosfets ? adjustable current limit ? monotonic output voltage at startup (prebias) ? output sink and source current capability ? adjustable soft-start ? thermal-overload protection ? output overvoltage protection ? thermally enhanced 6mm x 6mm tqfn package (4w) MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ________________________________________________________________ maxim integrated products 1 in pok output enable input bst lx v in = 12v v out = 1.2v/25a pgnd phase/refo comp en/slope freq ss gnd ilim MAX8686 refin rs+ rs- cs+ cs- pok typical application circuit ordering information 19-4113; rev 0; 5/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX8686etl+ -40c to +85c 40 tqfn-ep* + denotes a lead-free package. * ep = exposed pad. pin configuration appears at end of data sheet.
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v ina = 12v, vl = avl, v refin = 1v, v rs+ - v rs- = 1v, v rs- = 0v, v en/slope = 1.25v, v cs+ = v cs- = 1v, r ilim = 122k ? , c vl = 1f, c avl = 0.22f, c freq = 270pf, t a = +25c, unless otherwise noted.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, ina to pgnd.....................................................-0.3v to +22v bst, dh to lx...........................................................-0.3v to +6v bst to pgnd..........................................................-0.3v to +28v lx to pgnd...........................-0.3v to (v in + 0.3v) (-2v for 50ns) bst to vl................................................................-0.3v to +22v avl to gnd.................................................-0.3v to (v vl + 0.3v) comp, ilim, freq, phase/refo, rs+, rs-, pok, refin, cs+, cs- to gnd ..................................-0.3v to (v avl + 0.3v) vl to pgnd ..............................................................-0.3v to +6v en/slope to gnd ...................................................-0.3v to +6v rtn to pgnd to gnd to gfreq ..........................-0.3v to +0.3v in continuous current.....................................................20a rms lx continuous current ....................................................25a rms continuous power dissipation (t a = +70c) (note 1) 40-pin tqfn (derate 50mw/c above +70c) ..........4000mw jc (thermal resistance from junction to exposed pad) (note 1) ......................................................................3.5c/w jt (thermal resistance from junction to top) (note 1) ...3.9c/w operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c parameter conditions min typ max units general operating input-voltage range v ina = v in , t a = -40c to +85c 6 20 v operating input-voltage range v in = v ina = v vl = v avl , t a = -40c to +85c 4.5 5.5 v t a = +25c 450 in/ina shutdown supply current v en/slope = 0v, v in = v ina = 20v t a = +85c 500 a in/ina quiescent supply current v rs+ = 1.1v, no switching; v in = v ina = 20v, t a = -40c to +85c 5.5 6.6 ma rising, t a = -40c to +85c 4.2 4.35 4.45 avl undervoltage lockout trip level falling 4.03 v vl output voltage 6v v in = v ina 20v, 1ma i vl 30ma, t a = -40c to +85c 5.2 5.4 5.5 v soft-start (ss) ss shutdown resistance v en/slope = 0v (master mode) 20 100 ? ss soft-start current v ss = 0.4v and 1.1v, t a = -40c to +85c 19 25 31 a phase comparator and reference (phase/refo) reference output voltage measured at phase/refo (master mode), t a = -40c to +85c 3.267 3.300 3.333 v phase comparator offset v rs- = v avl (slave mode), v phase = 0.3v and 2.5v, t a = -40c to +85c -20 +20 mv refin input refin input bias current v refin = 0.7v or 3.3v -500 +500 na refin input voltage range 0 3.3 v note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial .
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v ina = 12v, vl = avl, v refin = 1v, v rs+ - v rs- = 1v, v rs- = 0v, v en/slope = 1.25v, v cs+ = v cs- = 1v, r ilim = 122k ? , c vl = 1f, c avl = 0.22f, c freq = 270pf, t a = +25c, unless otherwise noted.) (note 2) parameter conditions min typ max units error amplifier v refin = 3.3v 3.267 3.3 3.333 remote-sense accuracy (including error amplifier offset) measure as v rs+ - v rs- (t a = -40c to +85c) v refin = 0.7v 0.693 0.7 0.707 v transconductance t a = -40c to +85c 1.1 1.7 2.6 ms comp source current v rs+ - v rs- = 1.3v 220 300 a comp sink current v rs+ - v rs- = 0.7v 220 300 a comp shutdown resistance v en/slope = 0v 20 100 ? rs+/rs- input leakage current 0.2 1.5 a rs+ input common-mode range v in = v ina = v vl = v avl = 4.5v, v rs- = 100mv 0 3.4 v rs- input common-mode range -100 +100 mv current-sense amplifier input offset voltage measure at cs+ and cs-, v cs+ = v cs- = 0.7v and 5.5v (t a = -40c to +85c) -1.5 +1.5 mv current-sense amplifier gain v cs- = 0 to 5v, v cs+ - v cs- = 30mv, t a = -40c to +85c 29.0 30.5 32.0 v/v input bias current v cs+ = v cs- = 5.5v and 0v -4 +4 a current limit ilim output current v ilim = 2v, t a = -40c to +85c 9 10 11 a r ilim = 122k ? 16 20 23 current-limit threshold measure as v cs+ - v cs- (t a = -40c to +85c) r ilim = 275k ? 38 45 52 mv comp clamp voltage high r ilim = 275k ? , v refin = 3.3v, v rs+ - v rs- = 2v 3.6 3.8 4.0 v comp clamp voltage low v refin = 3.3v, v rs+ - v rs- = 3.35v 0.54 0.6 0.66 v maximum peak positive current threshold r ilim = 275k ? , no slope compensation 54 mv
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v ina = 12v, vl = avl, v refin = 1v, v rs+ - v rs- = 1v, v rs- = 0v, v en/slope = 1.25v, v cs+ = v cs- = 1v, r ilim = 122k ? , c vl = 1f, c avl = 0.22f, c freq = 270pf, t a = +25c, unless otherwise noted.) (note 2) note 2: specifications to t a = -40c are guaranteed by design and not production tested. parameter conditions min typ max units oscillator (freq) source current v freq = 2v, t a = -40c to +85c 480 500 520 a c freq = 180pf 0.8 1 1.2 mhz switching frequency c freq = 580pf 240 300 360 khz minimum on-time 100 ns freq discharge resistance 10 50 ? ramp peak voltage 2.60 v avl /2 2.85 v slope compensation (en/slope) v slope range 1.25 2.50 v slope source current 81012a thermal protection thermal shutdown rising temperature 160 c thermal-shutdown hysteresis 30 c power-ok (pok) v out rising 87 90 93 pok threshold v out falling 87 %v out pok output voltage low v rs+ - v rs- = 0.8v, i pok = 2ma 25 200 mv pok leakage current v pok = 5.5v 0.001 1 a overvoltage output protection (ovp) overvoltage fault trip level v refin = 3.3v, v rs+ rising, percentage of v out in regulation 115 120 125 % enable (en/slope) en logic-high 1.2 v en logic-low 0.7 v bst internal pmos on-resistance 8 ?
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase _______________________________________________________________________________________ 5 single-phase efficiency vs. load current MAX8686 toc01 load current (a) efficiency (%) 20 15 5 10 77.5 80.0 82.5 85.0 90.0 87.5 92.5 95.0 75.0 025 v out = 3.3v v out = 1.8v v out = 2.5v airflow = 300 lfm single-phase efficiency vs. load current (v in = 5v) MAX8686 toc02 load current (a) efficiency (%) 20 15 5 10 77.5 80.0 82.5 85.0 90.0 87.5 92.5 95.0 75.0 025 v out = 1.2v v out = 1.8v v out = 2.5v circuit of figure 3 airflow = 300 lfm efficiency vs. load current MAX8686 toc03 load current (a) efficiency (%) 17 14 8 11 80 81 82 83 85 84 86 87 79 520 270khz 379khz 467khz 564khz airflow = 300 lfm switching frequency vs. cfreq capacitance MAX8686 toc04 cfreq capacitance (pf) switching frequency (khz) 650 600 500 550 200 250 300 350 400 450 150 300 400 500 600 700 800 900 1000 1100 1200 1300 200 100 700 closed-loop frequency response (i out = 160a, 8 phases) frequency (hz) gain (db) 10 100 -40 -30 -20 -10 0 10 20 30 40 50 -50 phase (degrees) -144 -108 -72 -36 0 36 72 108 144 180 -180 11k MAX8686 toc05 phase gain output voltage vs. output current MAX8686 toc06 output current (a) output voltage (v) 20 15 5 10 1.2005 1.2010 1.2015 1.2020 1.2030 1.2025 1.2035 1.2040 1.2000 025 airflow = 300 lfm output voltage vs. input voltage MAX8686 toc07 input voltage (v) output voltage (v) 19 18 17 16 15 14 13 12 11 10 9 8 7 1.20 1.25 1.30 1.15 620 i out = 10a output load transient MAX8686 toc08 100 s/div v out 200mv/div ac-coupled i out 42a/div circuit of figure 4 airflow = 300 lfm soft-start with en control (i out = 10a) MAX8686 toc09 1ms/div en 2v/div ss 2v/div pok 5v/div v out 500mv/div circuit of figure 4 typical operating characteristics (v in = 12v, f sw = 500khz, single phase, circuit of figure 2, unless otherwise noted.)
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v in = 12v, f sw = 500khz, single phase, circuit of figure 2, unless otherwise noted.) soft-start with en control (i out = 10a) MAX8686 toc10 1ms/div en 2v/div ss 2v/div pok 5v/div v out 500mv/div circuit of figure 4 shutdown with en control (i out = 10a) MAX8686 toc11 200 s/div en 2v/div ss 5v/div pok 5v/div v out 500mv/div circuit of figure 4 shutdown with en control (i out = 100a) MAX8686 toc12 200 s/div en 2v/div ss 5v/div pok 5v/div v out 500mv/div circuit of figure 4 short-circuit protection MAX8686 toc13a 400 s/div i out 42a/div ss 500mv/div pok 5v/div v out 500mv/div short-circuit recovery MAX8686 toc13b 400 s/div i out 42a/div ss 500mv/div pok 5v/div v out 500mv/div current-sharing accuracy MAX8686 toc14 load current (a) phase current (a) 130 120 100 110 30 40 50 60 70 80 90 10 20 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 0 0 140 circuit of figure 4 airflow = 300 lfm lx_ switching waveform for phases 1, 2, 3, and 4 MAX8686 toc15 200ns/div lx1 5v/div lx2 5v/div lx3 5v/div lx4 5v/div circuit of figure 4
phase shedding from 6 phases to 2 phases (i out = 30a) MAX8686 toc18 1 s/div ps 2v/div lx1 10v/div lx5 10v/div lx2 10v/div circuit of figure 4 MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase _______________________________________________________________________________________ 7 phase recovery from 2 phases to 6 phases (i out = 30a) MAX8686 toc19 1 s/div ps 2v/div lx1 10v/div lx5 10v/div lx2 10v/div circuit of figure 4 safe operating area MAX8686 toc20 ambient temperature ( c) i out (a) 80 75 65 70 35 40 45 50 55 60 30 11 13 15 17 19 21 23 25 9 25 85 400 lfm 300 lfm 200 lfm 100 lfm 0 lfm t j = +125 c, v out = 1.2v safe operating area MAX8686 toc21 ambient temperature ( c) i out (a) 80 75 65 70 35 40 45 50 55 60 30 11 13 15 17 19 21 23 25 9 25 85 400 lfm 300 lfm 200 lfm 100 lfm 0 lfm t j = +125 c, v out = 3.3v lx_ switching waveform for phases 4, 5, 6, and 1 MAX8686 toc16 200ns/div lx4 5v/div lx5 5v/div lx6 5v/div lx1 5v/div circuit of figure 4 refo output vs. temperature MAX8686 toc17 temperature ( c) refo output (v) 80 70 60 50 40 30 20 10 0 -10 -20 -30 3.28 3.29 3.30 3.31 3.32 3.33 3.27 -40 90 typical operating characteristics (continued) (v in = 12v, f sw = 500khz, single phase, circuit of figure 2, unless otherwise noted.)
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 8 _______________________________________________________________________________________ pin description pin name function 1 cs- negative differential current-sense input. connect cs- to the output side of the inductor for lossless current sense or to the load side of the current-sense resistor. 2 cs+ positive differential current-sense input. connect cs+ to the inductor through an rc network for lossless current sense or to the inductor side of the current-sense resistor. 3 gfreq c freq capacitor return terminal. connect the frequency-setting capacitor c freq to gfreq as close as possible to the device. 4 en/slope enable and slope compensation input. connect a resistor from en/slope to gnd to set the desired slope compensation ramp voltage. an internal 10a current source pulls up en/slope. the device shuts down when the voltage at en/slope is less than 0.7v. connect en/slope to an open-drain or open-collector output for system enable or phase-shedding function. 5, 16 lx inductor connection. lx is high impedance during shutdown. 6 rtn power ground for low-side gate driver. connect rtn to pgnd plane at the return terminal of the in bypass capacitor. 7C15 pgnd power ground. low-side mosfet source connection. 17 n.c. no connection. not internally connected. 18C26 in power input. connect in to the input voltage source. connect input bypass capacitor from in to pgnd as close as possible to the device. connect in, ina, and vl together for 5v operation (see figure 3). 27 ina input of the internal vl linear regulator. bypass ina with a 0.1f capacitor to pgnd. 28 gnd analog ground 29 avl input voltage to the devices internal analog circuitry. connect avl to vl through a lowpass rc filter. 30 vl internal 5.4v linear regulator output. connect a ceramic capacitor of at least 1f from vl to rtn. ina is the input to this linear regulator. connect vl to ina when v ina is less than 5.5v. vl provides power for the mosfet drivers. 31 bst boost capacitor connection. connect a 0.22f ceramic capacitor from bst to lx. 32 pok power-good output. pok is an open-drain output that is high impedance when the output voltage is at its nominal regulated voltage. the pok rising threshold is 90% of the reference voltage at refin. pok is internally pulled low during shutdown. connect pok to gnd for slave mode operation.
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase _______________________________________________________________________________________ 9 pin description (continued) pin name function 33 freq frequency-setting input. connect a capacitor from freq to gfreq to set the switching frequency. the triangle ramp runs between 0 and avl/2. in multiphase applications, connect freq of the master and all slave devices together. freq is internally pulled to gfreq during shutdown. 34 ss soft-start input. for master-mode or single-phase operation, connect a capacitor from ss to gnd to set the soft-start time. a 25a internal current source charges the capacitor. ss is pulled to gnd in shutdown. connect ss to gnd for slave mode operation. 35 ilim analog programmable current limit. connect a resistor from ilim to gnd to set the current limit. a 10a current source through this resistor sets the current-limit threshold. in multiphase applications, connect ilim of the master and all slave devices together. 36 refin voltage error-amplifier reference input. for master-mode or single-phase operation, connect refin to phase/refo through a resistor-divider to set the output voltage from 0 to 3.3v. to use an external reference, connect refin to the system reference voltage, and use an rc network at refin to implement soft-start if the external reference does not provide this function. connect refin to gnd for slave mode operation. 37 p h as e /re fo phase selection input/reference voltage output. for single-phase or master-mode operation, the 3.3v output with 1% accuracy can be used as a reference voltage. for multiphase operation, connect phase/refo of each slave device to the center tap of a resistor-divider from the master avl to gnd. the resistor values are selected to set phase delay between phases. the pwm cycle starts 60ns after the rising edge of v freq crosses v phase . 38 comp compensation and output of the voltage-error amplifier. connect a type ii compensation network at comp. comp is internally pulled to gnd in shutdown. in multiphase applications, connect comp of the master and all slave devices together. 39 rs+ positive input of the output-voltage remote sense. for master-mode or single-phase operation, connect rs+ to the output-voltage sense point at the load. connect rs+ to avl (slave) for slave mode operation. 40 rs- negative input of the output-voltage remote sense. for master-mode or single-phase operation, connect rs- to the remote ground at the load. connect rs- to avl (slave) for slave mode operation. gnd_ep ground exposed paddle. connect gnd_ep to gnd. in_ep input exposed paddle. connect in_ep to in. lx_ep lx exposed paddle. connect lx_ep to lx.
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 10 ______________________________________________________________________________________ vl 500 a s2 to s4 pgnd rtn 10 a lx in level shift bst ina uvlo thermal shdn ramp generator 5.4v ldo generator pwm control logic current-limit control logic voltage reference slave mode detection slave mode = s1, s2, s3, s5, s6 open master mode = s1, s2, s5, s6 close 10 a avl freq uv ov phase/refo v ref soft-start circuitry en/slope en/slope vl avl ss s6 clock generator 0.9 1.2 refin fb pok en/slope g m error amplifier pwm comparator peak current- limit comparator s1 s3 s4 avl avl s5 v sum refin rs+ rs- fb comp cs+ cs- slope comp 1/2 current- sense amplifier 30.5 30.5 ilim gnd MAX8686 gfreq functional diagram
detailed description dc-dc converter control architecture the MAX8686 step-down regulator uses a pwm, cur- rent-mode control scheme. an internal transconduc- tance amplifier establishes an integrated error voltage. the heart of the pwm controller is a pwm comparator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus an adjustable slope-compensation ramp, which is summed with the current signal to ensure stability. at each rising edge of the internal clock, the internal high- side mosfet turns on until the pwm comparator trips or the maximum duty cycle is reached. during this on- time, current ramps up through the inductor, storing energy in the inductor while sourcing current to the output. the current-mode feedback system regulates the peak inductor current as a function of the output-voltage error signal. the circuit acts as a switch-mode transcon- ductance amplifier and pushes an output lc filter pole normally found in a voltage-mode pwm to a higher fre- quency. see the functional diagram . during the second half of the cycle, the internal high-side mosfet turns off and the internal low-side mosfet turns on. the inductor releases the stored energy as the current ramps down, providing current to the load. the output capacitor stores charge when the inductor cur- rent exceeds the required load current and discharges when the inductor current is lower, smoothing the volt- age across the load. under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the current-limit circuit section), the high-side mosfet is turned off immediately and the low-side mosfet is turned on and remains on to let the inductor current ramp down until the next clock cycle. under severe-overload or short-circuit conditions, the foldback/hiccup current limit is enabled to reduce power dissipation. the MAX8686 operates in a forced-pwm mode. the converter maintains a constant switching frequency, regardless of load, to allow for easier filtering of the switching noise. internal linear regulator (vl) the MAX8686 contains an internal ldo regulator that provides a 5.4v supply for the mosfet gate drivers. connect at least a 1f ceramic capacitor from vl to rtn. vl also provides power to the internal analog cir- cuit through avl. connect an rc lowpass filter (r = 10 ? , c = 0.22f) from vl to avl. undervoltage lockout when avl drops below 4.03v, the MAX8686 assumes that the supply voltage is too low to make valid deci- sions, so the undervoltage-lockout (uvlo) circuitry inhibits switching and turns off both power mosfets. when avl rises above 4.35v, the regulator enters the startup sequence and then resumes normal operation. when operating in a multiphase configuration, the avl of all the devices must exceed the uvlo threshold before any switching begins. this is achieved through the shared ilim pin, which is pulled low in uvlo. startup, soft-start, and prebias operation the internal soft-start circuitry gradually ramps up the reference voltage in order to control the rate of rise of the output voltage and reduce input surge currents dur- ing startup. the soft-start time is determined by the value of the capacitor from ss to gnd and is approxi- mately equal to 50ms per microfarad of the capacitor. in addition, the MAX8686 features monotonic output- voltage rise (prebias); therefore, both power mosfets are kept off if the voltage between the remote sense input (rs+, rs-) is higher than the voltage at refin. this allows the MAX8686 to start up into a prebiased output without pulling the output voltage down. before the MAX8686 can begin the soft-start and power-up sequence, the following conditions must be met: avl exceeds the 4.35v uvlo threshold, en is at logic-high, and the thermal limit is not exceeded. reference output (phase/refo)/reference input (refin) the reference voltage refo can be used to set the out- put voltage by scaling this voltage down with a resistive divider and using it as the input voltage to the reference input, refin. the 3.3v reference voltage is 1% accurate over temperature and can source up to 20a. the reference input refin allows the reference value of the device to be set by an external reference. in most applications, the 3.3v voltage with 1% accuracy from the phase/refo pin should be used as the reference. this can be achieved by dividing the 3.3v voltage to the desired output voltage. MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 11
MAX8686 for using an external reference on refin, ss needs to be tied to refin either directly or indirectly through a resistor for soft-start. for refin voltage lower than 1.25v, connect a resistor between ss and refin such that the voltage drop across the resistor due to the soft- start current (31a max) coming out of ss, causing the final ss voltage to be at least 1.25v (see figure 1a). the external reference should be able to sink at least 31a. calculate r refin as follows: where v ext is the external reference voltage. in a multiphase converter, only refin of the master device is connected to a reference voltage, and the refin of all slave devices should be tied to gnd. the refin also allows for coincident voltage tracking of multiple converters during power-up/power-down by applying the same voltage on refin of the master device in each converter. enable, phase shedding, and slope compensation input (en/slope) an internal 10a current source pulls the en/slope input high. the device shuts down when the voltage at the en/slope falls below 0.7v. by connecting an open-drain or open-collector switch to the en/slope, this pin can be used to enable/disable a single-phase or multiphase converter system. a separate system signal can be used to shed some phases of the converter at light load to eliminate all the power loss from these phases and thus improve the sys- tem efficiency. the phase shedding signal is connected to the en/slope pins of the slave devices to be shed. the right timing of the phase shedding signal from the system is critical for the safe operation of the multiphase converter. only after the load current drops below a cer- tain level, should the phase shedding signal become high. when the open-drain or open-collector switch is logic-low, it shuts down the slave phases connected to the switch to reduce power loss. before the load current increases to a certain level, the phase shedding signal should become logic-high to release the en/slope of these slave devices, thus turning these phases back on again to prepare for the higher load current. a minimum load of 2a per phase in the remaining phases is required for the shedded phase(s) to turn on. the transfer function of the power stage is different with a different number of phases. as the number of phases increases, the power stage gain increases. the compen- sation network should be designed such that the convert- er is always stable with the maximum number of phases. the en/slope input is also used to set the slope com- pensation ramp voltage by connecting a resistor from this input to gnd. the slope compensation is used to stabi- lize the converters when the duty cycle is more than 40%. high-side gate-drive supply (bst) a flying capacitor between bst and lx generates the gate-drive voltage for the internal high-side n-channel mosfet. when the low-side mosfet is turned on, the capacitor is charged by vl to 5.4v minus the drop across the internal boost switch. when the low-side mosfet is turned off, the stored voltage of the capaci- tor is stacked above lx to provide the necessary turn- on voltage (v gs ) for the high-side mosfet. an internal switch between bst and the internal high-side mosfets gate closes to turn the mosfet on. current-sense amplifier the current-sense circuit amplifies the differential current- sense voltage (v cs+ - v cs- ). this amplified current-sense signal and the internal-slope-compensation signal are summed (v sum ) together and fed into the pwm com- parators inverting input. the high-side mosfet is tu rned on by the clock in the device and is shut off when v sum exceeds the error-amplifier output voltage (v comp ) at the noninverting input of the pwm comparator. the dif- ferential current sense is also used to provide peak inductor current limiting. the limit can be set by adjust- ing the analog current-limit input (ilim). the current-sense amplifier is used to measure the cur- rent across the inductor by connecting to the inductor through an rc network for lossless current sensing or connecting to a current-sense resistor for higher accu- racy. the input common-mode voltage range of the current-sense amplifier is from 0 to 5.5v. r v a refin ext . = ? 125 19 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 12 ______________________________________________________________________________________ MAX8686 refin r refin v ext ss figure 1a. using an external reference
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 13 current-limit circuit the current-limit threshold is set by a resistor between ilim and gnd. under soft-overload conditions, when the peak inductor current exceeds the selected current limit, the high-side mosfet is turned off immediately and the low-side mosfet is turned on and remains on to let the inductor current ramp down until the next clock cycle. the converter does not stop switching and the output voltage regulation is not guaranteed. under severe-overload or short-circuit conditions, the foldback and hiccup current limit is simultaneously activated to reduce power dissipation in the inductor, internal power mosfets, and the upstream power source. thus, the circuit can withstand short-circuit conditions continu- ously without causing overheating of any component. if the device experiences a persistent overload condition, the device will autoretry with a soft-start. the converter will resume normal operation after the overload condi- tion is removed. the current-limit input is also used to communicate faults between the devices in a multiphase configuration. with any fault on the slave or master device (such as uvlo or overtemperature), the ilim input is pulled low, which causes the other devices to turn off both mosfets. current sharing accurate current sharing is required in a multiphase con- verter to prevent some phases from overheating during soft-start, steady-state, and load transient. for a convert- er with current-mode control, the current is proportional to the error-amplifier output in the voltage feedback loop. the error-amplifier output (comp) of the master is con- nected to the current comparator input of all slave devices. the current-sharing accuracy is determined by the tolerances of the inductance and inductor dcr, the input offset voltage, the gain of the current-sense ampli- fiers, and the slope compensation circuits. the peak current-mode control is an open-loop current- sharing scheme, and therefore no compensation for current sharing is needed and no stability issue exists. switching frequency and ramp generation (freq) the MAX8686 has an adjustable internal oscillator that can be set to any frequency from 300khz to 1mhz. to set the switching frequency, connect a capacitor from the freq to gfreq (see setting the switching frequency section). a triangle ramp from 0 to avl/2 is generated across freq capacitor. in a multiphase application, the capacitor needs to be connected to the master device. the freq inputs of the master and slave devices need to be connected together. freq is internally pulled down to gfreq during shutdown. phase selection input (phase/refo) for single-phase or master device operation, the phase/refo can be used as a reference for the con- verter output voltage (see the reference output (phase/refo)/reference input (refin) section). for multiphase operation, connect the phase/refo of each slave device to the center tap of the resistor- divider from avl of the master to gnd. the resistor val- ues are selected to set delay time between phases (see the calculating the phase voltage section). the pwm clock cycle of slave devices starts 60ns after the rising edge of the voltage at freq crosses the voltage at phase/refo. the pwm clock cycle of the master device starts at the beginning of the ramp. remote sense input (rs+, rs-) for single-phase or master operation, connect rs+ to the sense point at the load and rs- to the gnd sense point of the load. the connections should be at the out- put regulation point to eliminate the voltage-sense error caused by voltage drop between the device and load. the rs+ and rs- traces should be laid out in parallel to reduce noise coupling. a common-mode filter to each sense trace should be added if further noise reduction is needed. for an output voltage higher than 3.3v, tie phase/refo to refin and use a resistor-divider from the output regulation point to the remote sense inputs (rs+, rs-), as shown in figure 1b. for multiphase operation, connect rs+ and rs- to avl (slave) to select the slave mode. MAX8686 v out load rs+ refin r1 r2 phase/refo rs- figure 1b. output voltage above 3.3v
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 14 ______________________________________________________________________________________ overvoltage protection the MAX8686 provides output overvoltage protection (ovp). the ovp threshold is set at 20% above the set output voltage. when the overvoltage condition is expe- rienced, the output is latched to pgnd through the low- side mosfet. to clear the latch, the en/slope input should be pulled logic-low and then reinitialized. the output starts up in a soft-start mode. to prevent the overvoltage protection from initializing during power-up, some consideration should be given to the soft-start timing to reduce the inrush current. in addition, the proper compensation network would prevent overshoot during power-up. power-ok (pok) signal pok is an open-drain output that monitors the output volt- age. when the output is above 90% of its nominal regula- tion voltage, pok goes high impedance. there is a 3% hysteresis to prevent the pok output from chattering. the pok indicator can be used for sequencing. thermal-overload protection thermal-overload protection limits total power dissipa- tion in the MAX8686. when the junction temperature exceeds +160c, an internal thermal sensor shuts down the device, allowing it to cool down. the thermal sensor turns the device on again after the junction tem- perature cools by 30c, resulting in a pulsed output during continuous thermal-overload conditions. see figures 2, 3, and 4. bst 31 32 33 34 35 36 37 38 39 40 + lx gfreq power- ok c1 330pf c17 1 f c18 0.22 f c16 0.22 f c15 0.1 f c3 10nf c4 2.2nf c4 150pf r5 5.6k ? r1 10k ? r16 162k ? r3 200k ? r4 115k ? r2 150k ? c13 10 f c12 10 f c6 220 f c7 220 f c14 1 f c11 10 f input 6v to 20v 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx gfreq refin phase/refo freq in n.c. lx pgnd u1 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r11 270 ? r13 10 ? enable (en) output 1.2v/25a l11 0.56 h c2 15pf r12 10 ? MAX8686 r14 270 ? figure 2. single-phase application circuit operating at v in = 12v
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 15 bst 31 32 33 34 35 36 37 38 39 40 lx gfreq power- ok c1 330pf c17 1 f c18 0.22 f c16 0.22 f c15 0.1 f c3 10nf c5 2.2nf c4 150pf r5 5.6k ? r16 162k ? r3 200k ? r4 115k ? r2 130k ? c13 10 f c12 10 f c6 220 f c7 220 f c14 1 f c11 10 f input 4.5v to 5.5v 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx gfreq refin phase/refo freq in n.c. lx pgnd u1 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r11 270 ? r13 10 ? r1 10k ? enable (en) output 1.2v/25a l11 0.56 h MAX8686 r14 270 ? c2 15pf + figure 3. single-phase application circuit operating at v in = 5v
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 16 ______________________________________________________________________________________ bst 31 32 33 34 35 36 37 38 39 40 lx1 gfreq power ok c1 270pf c17 1 f c18 0.22 f c16 0.22 f c15 0.1 f c2 33nf c4 2.2nf c3 150pf r5 5.6k ? r16 162k ? r3 200k ? r4 115k ? r2 150k ? c12 10 f c11 10 f input: 6v-20v 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx1 gfreq refin phase/refo freq in n.c. lx pgnd u1 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r13 10 ? r1 10k ? enable (en) output: 1.2v/150a r46 162k ? r12 10 ? c42 10 f c71?94 100 f x 24 c41 10 f MAX8686 bst 31 32 33 34 35 36 37 38 39 40 phase shedding (ps) lx4 c47 1 f c48 0.22 f c46 0.22 f c45 0.1 f c49 10pf r45 16.5k ? r44 54.9k ? 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx4 gfreq refin phase/refo freq in n.c. lx pgnd u4 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r43 10 ? avl4 avl1 avl5 r42 10 ? MAX8686 r56 162k ? c52 10 f c51 10 f c54 1 f r51 270 ? l51 0.56 h bst 31 32 33 34 35 36 37 38 39 40 lx5 c57 1 f c58 0.22 f c56 0.22 f c55 0.1 f c59 10pf r55 16.5k ? r54 35.7k ? 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx5 gfreq refin phase/refo freq in n.c. lx pgnd u5 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r53 10 ? avl5 avl1 avl5 r52 10 ? MAX8686 r66 162k ? c62 10 f c61 10 f c64 1 f r61 270 ? l61 0.56 h bst 31 32 33 34 35 36 37 38 39 40 lx6 c67 1 f c68 0.22 f c66 0.22 f c65 0.1 f c69 10pf r65 16.5k ? r64 24.3k ? 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx6 gfreq refin phase/refo freq in n.c. lx pgnd u6 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r63 10 ? avl6 avl1 avl6 r62 10 ? MAX8686 r26 162k ? c2 10 f c21 10 f c24 1 f r21 270 ? l21 0.56 h bst 31 32 33 34 35 36 37 38 39 40 lx2 c27 1 f c28 0.22 f c26 0.22 f c25 0.1 f c29 10pf r25 16.5k ? r24 267k ? 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx2 gfreq refin phase/refo freq in n.c. lx pgnd u2 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r23 10 ? avl2 avl1 avl2 r22 10 ? MAX8686 r36 162k ? c32 10 f c31 10 f c34 1 f r31 270 ? l31 0.56 h bst 31 32 33 34 35 36 37 38 39 40 lx2 c37 1 f c38 0.22 f c36 0.22 f c35 0.1 f c39 10pf r35 16.5k ? r34 97.6k ? 30 29 28 27 26 25 24 23 22 21 pok ss ilim comp rs+ rs- lx3 gfreq refin phase/refo freq in n.c. lx pgnd u3 pgnd pgnd pgnd pgnd in in lx rtn pgnd pgnd pgnd en/slope gfreq cs+ cs- avl gnd ina in in in in in in vl pgnd 5 6 7 9 10 4 3 2 1 8 15 16 17 19 20 14 13 12 11 18 r33 10 ? avl3 avl1 avl2 r32 10 ? MAX8686 r57 270 ? c44 1 f r48 270 ? l41 0.56 h r47 270 ? r37 270 ? r67 270 ? r27 270 ? c14 1 f r11 270 ? l11 0.56 h r17 270 ? figure 4. multiphase application at v in = 12v
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 17 design procedures setting the output voltage to set the output voltage for the MAX8686, connect refin to the center of an external resistor-divider from phase/refo to gnd (r3 and r4 of figures 2, 3, or 4). the sum of r3 and r4 should exceed 165k ? . preselect r4 and calculate r3 using the following equation: where v out is the desired output voltage and 3.3v comes from the reference voltage (v phase/refo ). the resistor-divider should be placed as close as possible to refin. if an external reference is used, see the reference output (phase/refo)/reference input (refin) section for more details. inductor selection the output inductor is selected based on the desired amount of inductor ripple current. a larger inductance value minimizes output ripple current and increases efficiency but slows down the output-inductor-current slew rate during a load transient. lir is the ratio of rip- ple current to the total current per phase. for the best tradeoff of efficiency and transient response, an lir of 30% to 60% is recommended (lir = 0.3 to 0.6). choose a higher lir when more phases are used to take advantage of ripple-current cancellation. the inductor value is determined from: where f sw is the per-phase switching frequency, i out_max is the maximum-rated output current, d is the duty ratio (v out /v in ), n is the number of phases, and v out is the output voltage. the selected inductor should have low dc resistance, and the saturation cur- rent should be greater than the peak inductor current, i peak . i peak is found from: when the dc resistance (r dc ) of the output inductor is used for current sensing, the dc resistance should be selected to ensure a sufficient current-sense signal for robust current-mode control. the following equation can be used as a guideline. where r dc is the sense resistance value of the inductor or sense resistor at the highest operating temperature. it is also important to choose lower lir to keep the cur- rent-sense signal below 45mv, which is the maximum current limit: if this condition is not met, then the lir must be adjust- ed or the input signal to the current-sense amplifier must be scaled down with a resistor-divider. setting the switching frequency to set the switching frequency, connect a capacitor from freq to gfreq. calculate the capacitor value in microfarads from the following equation: where f sw is the desired switching frequency in kilo- hertz and c freq is the total capacitance in picofarads. the operating frequency range is from 300khz to 1mhz, so the capacitance at freq should be between 600pf and 180pf. parasitic capacitance from device pads and pcb layout should be deducted from the above calculation especially at high switching frequen- cies. in the estimation of parasitic capacitance, 15pf per phase should be used. setting the slope compensation for most applications where the duty cycle is less than 40%, set en/slope = 1.25v. for applications with a duty cycle greater than 40%, set the slope compensa- tion with a resistor (r slope ) from en/slope to gnd. calculate the r slope using the following formula: where r dc is the dc resistance of the inductor, v in_min is the minimum operating input voltage, and f sw is the switching frequency. r xr f xv slope dc sw xl out . . = ? 122 10 01 7 8 82 _ xv in min () c xf xf freq x sw sw . = ? ? 510 27 5 30 i n lir xr mv out max dc _ 1 2 45 + ? ? ? ? ? ? i n lir r mv out max dc _ 10 i i n lir peak out max =+ ? ? ? ? ? ? _ 1 2 l vdn lir f i out sw out max ? () _ 1 rr v out 34 33 1 = ? ? ? ? ? ? ? .
MAX8686 setting the peak current limit the peak current-limit threshold (v cs+ - v cs- ) is set by a resistor connected from ilim to gnd. an internal 10a current source flows through this resistor to set a voltage that is 61 times higher than the current-limit threshold. for example, a 300k ? resistor sets the cur- rent-limit threshold at (10a x 300k ? )/61 or 49mv: where r ilim is in kilohms, v th is in millivolts, and corre- sponds to the peak voltage across the sensing element (inductor resistance or current-sense resistor). this allows a maximum average dc output current of (ilim): where r dc is the dc resistance of the inductor or sense resistor and i p-p is the peak-to-peak inductor current. to ensure maximum output current, use the minimum value of v th from each setting and the maximum r dc values at the highest expected operating temperature. the dc resistance of the inductors copper wire has a +0.38%/c temperature coefficient. when using a sense resistor, the current through the sense resistor sets a voltage compared with the peak current limit. to provide a more efficient and lower cost design, the current can be measured through the inductor using a dcr method (voltage across the dc resistance of the inductor) as shown in figure 5. an rc circuit is connected across the inductor. the rc time constant is set to be 1.1 to 1.2 times the inductor time constant (l/r dc ). pick the value of c1 in the 1f to 4.7f range, and then calculate r1 from: r2 is added in some applications to scale down the current signal. r2 and lir should be selected to meet the following condition. calculating the phase voltage in the multiphase converter, the phases are interleaved to reduce the output voltage ripple. the master starts conduction at the beginning of the freq ramp. the phase delay time, t phase , is the conduction delay time of slaves from the master. determine the phase delay time as follows: where x is the number of the slave (x = 1 to 5 for 6 phase converters) f sw is the switching frequency per phase in kilohertz, and n is the total number of phases. calculate the phase voltage of each slave from: where c freq is the total capacitance (in picofarads) at freq (see the setting the switching frequency sec- tion). for better jitter immunity, v phase should be limit- ed between 0.3v and 2.5v. then determine resistor-divider for each slave. preselect more than 10k ? for phase resistor rx5 (x = 2 to 6, r25, r35, r45, r55, and r65) in figure 4, and cal- culate rx4 (r24, r34, r44, r54, and r64) as follows: input capacitor the input capacitor reduces the peak current drawn from the power source and reduces the noise and volt- age ripple on the input dc voltage bus caused by the circuits switching. the input capacitors must meet the rx vxrx v phase x phase x 5 4 54 1 1 . () () = ? ? ? v txx c phasex phasex freq = ? 510 30 8 t x fx xn phasex sw = 10 3 i n x lir xr x r rr out max dc _ 1 2 2 1 + ? ? ? ? ? ? + 2 2 45 mv r xl rxc dc 1 12 1 1 . = i v r i lim th dc pp = ? ? 2 vv v xr th cs cs ilim = ? = + ? 10 61 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 18 ______________________________________________________________________________________ MAX8686 v out l1 c1 r1 r2 lx cs+ cs- figure 5. current sense using the inductors dc resistance
ripple-current requirement (i rms ) imposed by the switching currents as defined by the following equations: for (n x d) 1: for (n x d) > 1. where n is the number of phases, d is the duty cycle, and i out_max is the maximum output current. use the minimum input voltage for calculating the duty cycle to obtain the worst-case input-capacitor rms rip- ple current. low-esr aluminum electrolytic, polymer, or ceramic capacitors should be used to avoid large volt- age transients at the input during a large step load change at the output. the ripple-current specifications provided by the manufacturer should be carefully reviewed for temperature derating. additional small- value, low-esl ceramic capacitors (1f to 10f with proper voltage rating) can be used in parallel to reduce any high-frequency ringing. output capacitor the minimum output capacitance, c out(min) , is required to meet load-dump requirements. the worst- case load dump is a sudden transition from full load current (i 2 out_max ) to minimum load current (i 2 out_min ). c out(min) is estimated based on energy balance from: where i 2 out_max and i 2 out_min are the initial and final values of the load current during the worst-case load dump, v init 2 is the voltage prior to the load dump, v fin is the steady-state voltage after the load dump, and v ov is the allowed voltage overshoot above v fin . the term (v fin + v ov ) represents the maximum transient output voltage reached during the load dump. the above equation is an approximation, and the output capacitance value obtained serves as a good starting point. the final value should be obtained from actual measurements. for ceramic output capacitors, the out- put capacitor requirement is determined mostly by load dump requirements due to their low esr and esl. see figures 7 and 8. compensation design the MAX8686 uses an internal transconductance error amplifier whose output compensates the control loop. the external inductor, output capacitor, compensation c l n ii vv out min out max out min fin ov () __ ? () + ( 22 ) ) ? 2 2 v init idi nd nd rms out max = ? ? _ () 32 1 2 idi nd rms out max = ? _ 1 1 MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 19 MAX8686 r c c c comp c f figure 6. compensation components gain (db) frequenc (hz) fp mod fz mod f c closed loop error amplifier 0 voltage- divider power modulator figure 7. simplified gain plot for the f zmod > f c case gain (db) frequenc (hz) fp mod fz mod f c 0 power modulator closed loop error amplifier voltage- divider figure 8. simplified gain plot for the f zmod < f c case
MAX8686 resistor, and compensation capacitors determine the loop stability. the inductor and output capacitor are chosen based on performance, size, and cost. additionally, the compensation resistor and capacitors are selected to optimize control-loop stability. the compo- nent values, shown in figures 2, 3, and 4, yield stable operation over the given range of input-to-output voltages. the regulator uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. the voltage drop across the dc resistance of the inductor or the alter- nate series current-sense resistor is used to measure the inductor current. current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor resulting in a smaller phase shift and requiring a less elaborate error-amplifi- er compensation than voltage-mode control. a simple series r c and c c is all that is needed to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering. for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a nonceramic output-capacitor loop, add another compensation capacitor from comp to gnd to cancel this esr zero. see figure 6. the basic regulator loop is modeled as a power modula- tor, an output feedback divider, and an error amplifier. the power modulator has dc gain set by g mc x r load , with a pole and zero pair set by r load , the output capac- itor (c out ), and its equivalent series resistance (esr). below are equations that define the power modulator: where r load = v out /[i out(max) /n], f sw is the switch- ing frequency, l is the output inductance, g mc = 1/(a vcs x r dc ), where a vcs is the gain of the current- sense amplifier (30.5 typ), r dc is the dc resistance of the inductor, the duty cycle d = v out /v in . k s is a slope compensation factor calculated from the following equation: find the pole and zero frequencies created by the power modulator as follows: when c out comprises n identical capacitors in paral- lel, the resulting c out = n x c out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of like capacitors is the same as for an individual capacitor. the transconductance error amplifier has a dc gain, g ea(dc) = g mea x r o , where g mea is the error-amplifi- er transconductance, which is equal to 1.7ms, and r o is the output resistance of the error amplifier, which is 30m ? . a dominant pole (f pdea ) is set by the compen- sation capacitor (c c ), the amplifier output resistance (r o ), and the compensation resistor (r c ); a zero (f zea ) is set by the compensation resistor (r c ) and the com- pensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c ). thus: the crossover frequency, f c , should be much higher than the power-modulator pole f pmod . also, f c should f crr f cr f pdea coc zea cc pea = + = = 1 2 1 2 1 2 () c cr fc f c esr zmod out = 1 2 f n rc n lf c kd pmod load out sw out s = + ? 22 1 () ). ? [] ? ? ? ? ? ? 05 k vxv fxlxv s out in min sw in =+ ? ? 1 0 182 . ( _ v v out ) gg r r lf kd mod dc mc load load sw s () = + ? () () ? 110 . .5 ? ? ? ? ? ? ? ? ? ? single/multiphase, step-down, dc-dc converter delivers up to 25a per phase 20 ______________________________________________________________________________________
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase ______________________________________________________________________________________ 21 be less than or equal to 1/5 the switching frequency. select a value for f c in the range: the feedback voltage-divider gain (v ref /v out ) should be included for an output voltage higher than 3.3v, where v refin is equal to 3.3v. at the crossover frequency, the total loop gain must equal 1, and is expressed as: for the case where f zmod is greater than f c : then r c can be calculated as: where g mea = 1.7ms. the error-amplifier compensation zero formed by r c and c c should be set at the modulator pole f pmod . calculate the value of c c as follows: if f pmod is less than 5 x f c , add a second capacitor c f from comp to gnd. the value of c f is: as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. for the case where f zmod is less than f c : the power modulator gain at f c is: the error-amplifier gain at f c is: r c is calculated as: where g mea = 1.7ms. c c is calculated from: c f is calculated from: the current-mode control model on which the above design procedure is based requires an additional high- frequency term, g s (s), to account for the effect of sam- pling the peak inductor current. the term g s (s) produces additional phase lag at crossover and should be modeled to estimate the phase margin obtainable by the selected compensation components. as a final step, it is useful to plot the db gain and phase of the following loop-gain transfer function and check the obtained phase margin. a phase margin of at least 45 is recommended: where the sampling effect quality factor is: q kd c s = ?? [] 1 105 (().) gs s qf s f s csw sw () = + + () ? ? ? ? ? ? ? ? 1 1 2 2 gs r gmc r lf ks d loop load load sw () () = + ? () ? 110 . . (/ ) (/ ) 5 12 12 ? ? ? ? ? ? ? ? ? ? + + sf sf zmod pmod ( (/ ) (/ )(/ ) 12 12 12 + ++ sf sf sf zea pea pdea g grov v gs mea refin out s () c rf f czmod = 1 2 c fr c pmod c = 1 2 r v v f gg f c out fb c mea mod fc zmod = () ggr f f ea fc mea c zmod c () = gg f f mod fc mod dc pmod zmod () ( ) = c rf f czmod = 1 2 c fr c pmod c = 1 2 r v gv g c out mea refin mod fc = () ggr gg f f ea fc mea c mod fc mod dc pmod c () () ( ) = = gg v v ea fc mod fc refin out () () = 1 ff f pmod c sw << 5
MAX8686 single/multiphase, step-down, dc-dc converter delivers up to 25a per phase maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. applications information pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. follow these guidelines for good pcb layout: 1) place ic decoupling capacitors as close to the ic pins as possible. separate the power and analog ground planes. place the input ceramic decoupling capacitor directly across and as close as possible to in and pgnd. this is to help contain the high switching current within this small loop. 2) for output current greater than 10a, a four-layer pcb is recommended. pour an analog ground plane in the second layer underneath the ic to min- imize noise coupling. 3) connect input and output capacitor to the pgnd plane and the vl capacitor to rtn. connect all analog signals to gnd. the frequency-setting capacitor should be connected to gfreq. 4) connect pgnd, gnd, and rtn at the return path of the input bypass capacitor. 5) signals shared by the master and slave (ilim, comp, and freq) should not run close to switch- ing signals. 6) place the inductor current-sense resistor and capacitor as close to the inductor as possible. make a kelvin connection to minimize the effect of pcb trace resistance. 7) connect the exposed pad sections to the corre- sponding ic pins and allow sufficient copper area to help cooling the device. 8) place the refin and compensation components as close to the ic pins as possible. 9) connect remote-sense input rs+ and rs- directly to the load voltage regulation point and use kelvin connection for the two traces. 10) refer to the MAX8686 evaluation kit for an exam- ple layout. package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 40 tqfn t4066m-1 21-0177 40 tqfn t4066mn-1 21-0177 MAX8686 tqfn + top view 35 36 34 33 12 11 13 cs+ en/slope lx rtn pgnd 14 cs- ina in in gnd avl vl in in 12 ss 4567 27 28 29 30 26 24 23 22 ilim refin in n.c. lx pgnd gfreq in 3 25 37 phase/refo pgnd 38 39 40 comp rs+ rs- pgnd pgnd pgnd freq 32 15 in pok 31 16 17 18 19 20 in gnd_ep in_ep lx_ep pgnd pgnd pgnd in 8910 21 bst pin configuration chip information process: bicmos

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